The present invention relates to a technique for signal transmission between elements (e.g., between digital circuits including CMS's or between their functional blocks) such as multiprocessors or memories in an information processing apparatus and more particularly, to a technique for speeding up data bus transfer of a plurality of elements connected to an identical transmission line. More particularly, the present invention concerns a bus for connection between a plurality of memory modules and a memory controller as well as a system using the bus.
In order to transmit data at a high speed on a wiring bus through which a multiplicity of nodes such as a plurality of dynamic random access memory modules are connected to a memory controller, a transmission delay time based on the length of the wired buses cannot be negligible. SynchLink, “A Proposal for an Implementation of IEEE P1596.4 (Ramlink) Optimized for small (single board) Memory Systems”, Mar. 23, 1995; WO99/48260 specification Publication; JP-A-7-141079; and Betty Prince, “High Performance Memories”, John Wiley & Sons Ltd., 1995, p205-209, disclose a vernier for accommodating a time difference caused by the length of wiring lines between a clock signal which determines a timing reference of memory access and a read or write data signal in a memory bus wiring system, that is, a phase difference as well as signaling for improving a clock signal propagation direction. U.S. patent application Ser. No. 09/429,441 is directed to a directional coupling bus system.